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ACM Transactions on Programming Languages and Systems (TOPLAS), Volume 19 Issue 4, July 1997

Nesting of reducible and irreducible loops
Paul Havlak
Pages: 557-567
DOI: 10.1145/262004.262005
Recognizing and transforming loops are essential steps in any attempt to improve the running time of a program. Aggressive restructuring techniques have been developed for single-entry (reducible) loops, but restructurers and the dataflow and...

Interprocedural control flow analysis of first-order programs with tail-call optimization
Saumya K. Debray, Todd A. Proebsting
Pages: 568-585
DOI: 10.1145/262004.262006
Knowledge of low-level control flow is essential for many compiler optimizations. In systems with tail-call optimization, the determination of interprocedural control flow is complicated by the fact that because of tail-call optimization,...

A refinement calculus for the synthesis of verified hardware descriptions in VHDL
Peter T. Breuer, Carlos Kloos Delgado, Andrés López Marín, Natividad Martínez Madrid, Luis Sánchez Fernández
Pages: 586-616
DOI: 10.1145/262004.262007
A formal refinement calculus targeted at system-level descriptions in the IEEE standard hardware description language VHDL is described here. Refinement can be used to develop hardware description code that is “correct by...

Utilizing symmetry when model-checking under fairness assumptions: an automata-theoretic approach
E. A. Emerson, A. P. Sistla
Pages: 617-638
DOI: 10.1145/262004.262008
One useful technique for combating the state explosion problem is to exploit symmetry when performing temporal logic model checking. In previous work it is shown how, using some basic notions of group theory, symmetry may be exploited for the...